1

Data sheet acquired from Harris Semiconductor

SCHS154

Features

• CD74HC161, CD74HCT161 4-Bit Binary Counter,

Asynchronous Reset

• CD74HC163, CD74HCT163 4-Bit Binary Counter,

Synchronous Reset

• Synchronous Counting and Loading

• Two Count Enable Inputs for n-Bit Cascading

• Look-Ahead Carry for High-Speed Counting

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Description

The Harris CD74HC161, CD74HCT161, CD74HC163 and

CD74HCT163 are presettable synchronous counters that

feature look-ahead carry logic for use in high-speed

counting applications. The CD74HC161 and CD74HCT161

are asynchronous reset decade and binary counters,

respectively; the CD74HC163 and CD74HCT163 devices

decade and binary counters, respectively and are reset

synchronously with the clock. Counting and parallel

presetting are both accomplished synchronously with the

negative-to-positive transition of the clock.

A low level on the synchronous parallel enable input, SPE,

disables counting operation and allows data at the P0 to P3

inputs to be loaded into the counter (provided that the

setup and hold requirements for SPE are met).

All counters are reset with a low level on the Master Reset

input, MR. In the CD74HC163 and CD74HCT163 counters

(synchronous reset types), the requirements for setup and

hold time with respect to the clock must be met.

Two count enables, PE and TE, in each counter are

provided for n-bit cascading. In all counters reset action

occurs regardless of the level of the SPE, PE and TE inputs

(and the clock input, CP, in the CD74HC161 and

CD74HCT161 types).

If a decade counter is preset to an illegal state or assumes

an illegal state when power is applied, it will return to the

normal sequence in one count as shown in state diagram.

The look-ahead carry feature simplifies serial cascading of

the counters. Both count enable inputs (PE and TE) must

be high to count. The TE input is gated with the Q outputs

of all four stages so that at the maximum count the terminal

count (TC) output goes high for one clock period. This TC

pulse is used to enable the next cascaded stage.

Pinout

CD74HC161, CD74HCT161, CD74HC163, CD74HCT163

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

PACKAGE

PKG.

NO.

CD74HC161E

-55 to 125

16 Ld PDIP

E16.3

CD74HC161M

-55 to 125

16 Ld SOIC

M16.15

CD74HC163E

-55 to 125

16 Ld PDIP

E16.3

CD74HC163M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT161E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT161M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT163E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT163M

-55 to 125

16 Ld SOIC

M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to ob-

tain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or Harris

customer service for ordering information.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

MR

CP

P0

P1

P2

P3

GND

PE

Q0

Q1

Q2

Q3

TE

SPE

TC

February 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1550.1

CD74HC161, CD74HCT161,

CD74HC163, CD74HCT163

High Speed CMOS Logic

Presettable Counters

[ /Title

(CD74

HC161

,

CD74

HCT16

1,

CD74

HC163

,

CD74

HCT16

3)

/Sub-

ject

(High

Speed

CMOS

Logic

Preset-

table

Counte

rs)

/Autho

r ()

/Key-

words

(High

Speed

CMOS

Logic

Preset-

table

Counte

rs,

High

Speed