1

Data sheet acquired from Harris Semiconductor

SCHS221

Features

• Synchronous or Asynchronous Preset

• Cascadable in Synchronous or Ripple Mode

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Description

The

Harris

CD74HC40103

and

CD74HCT40103

are

manufactured with high speed silicon gate technology and

consist of an 8-stage synchronous down counter with a

single output which is active when the internal count is zero.

The 40103 contains a single 8-bit binary counter. Each has

control inputs for enabling or disabling the clock, for clearing

the counter to its maximum count, and for presetting the

counter either synchronously or asynchronously. All control

inputs and the TC output are active-low logic.

In normal operation, the counter is decremented by one

count on each positive transition of the CLOCK (CP).

Counting is inhibited when the TE input is high. The TC

output goes low when the count reaches zero if the TE input

is low, and remains low for one full clock period.

When the PE input is low, data at the P0-P7 inputs are

clocked into the counter on the next positive clock transition

regardless of the state of the TE input. When the PL input is

low, data at the P0-P7 inputs are asynchronously forced into

the counter regardless of the state of the PE, TE, or CLOCK

inputs. Input P0-P7 represent a single 8-bit binary word for

the 40103. When the MR input is low, the counter is

regardless of the state of any other input. The precedence

relationship between control inputs is indicated in the truth

table.

If all control inputs except TE are high at the time of zero

count, the counters will jump to the maximum count, giving a

counting sequence of 100 or 256 clock pulses long.

The 40103 may be cascaded using the TE input and the TC

output, in either a synchronous or ripple mode. These

circuits possess the the low power consumption usually

associated

with

CMOS

circuitry,

yet

have

speeds

comparable to low power Schottky TTL circuits and can drive

up to 10 LSTTL loads.

Ordering Information

PART NUMBER

PACKAGE

PKG.

NO.

CD74HC40103E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT40103E

-55 to 125

16 Ld PDIP

E16.3

CD74HC40103M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT40103M

-55 to 125

16 Ld SOIC

M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

November 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1596.1

CD74HC40103,

CD74HCT40103

High Speed CMOS Logic

8-Stage Synchronous Down Counters

[ /Title

(CD74H

C40103,

CD74H

CT4010

3)

/Sub-

ject

(High

Speed

CMOS

Logic 8-