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CDC536DL Folha de dados(PDF) 6 Page - Texas Instruments |
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CDC536DL Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 12 page CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS378F – APRIL 1994 – REVISED OCTOBER 1998 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT f lk Clock frequency When VCO is operating at four times the CLKIN frequency 25 50 MHz fclock Clock frequency When VCO is operating at double the CLKIN frequency 50 100 MHz Input clock duty cycle 40% 60% † After SEL 50 Stabilization time† After OE ↓ 50 µs Stabilization time† After power up 50 µs After CLKIN 50 † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Note 4 and Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT fmax 100 MHz Duty cycle Y 45% 55% tphase error‡ CLKIN ↑ Y –500 +500 ps Jitter(pk-pk) CLKIN ↑ Y 200 ps tsk(o)‡ 0.5 ns tsk(pr) 1 ns tr 1.4 ns tf 1.4 ns ‡ Thepropagationdelay, tphaseerror,isdependentonthefeedbackpathfromanyoutputtoFBIN.Thetphaseerror,tsk(o),andtsk(pk)specifications are only valid for equal loading of all outputs. NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. |
Nº de peça semelhante - CDC536DL |
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Descrição semelhante - CDC536DL |
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