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SLWS132 Folha de dados(PDF) 9 Page - Texas Instruments |
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SLWS132 Folha de dados(HTML) 9 Page - Texas Instruments |
9 / 46 page GRAYCHIP, INC. - 4 - APRIL 27, 1999 GC4014 QUAD RECEIVER CHIP DATA SHEET REV 0.6 This document contains information which may be changed at any time without notice each input sample, allowing input data rates down to 1/16th the clock rate. Zero padding also lowers the effective decimation ratio. For example, the minimum decimation is normally factor of 32. If the input data rate is 5 MSPS and the chip can be clocked at 40 MHz, then the zero pad function can be used to pad the 5 MSPS input data up by a factor of 8 to 40 MSPS. The minimum decimation of 32, once the zero padding is done, becomes a minimum decimation of 4 relative to the original 5 MSPS data. 3.3 THE DOWN CONVERTERS Each down converter uses an NCO and mixer to quadrature down convert a signal to baseband and then uses a 4 stage CIC1 filter and a two-stage decimate by 4 or 8 filter to lowpass filter and to isolate the desired signal. A block diagram of each filter is shown below: Figure 3. The Down Converter Channel The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 16,384. The CIC outputs are followed by a coarse gain stage and then followed by a two stage decimate by 4 or 8 filter. The coarse gain circuit allows the user to boost the gain of weak signals up to 42 dB in 6 dB steps. The first stage of the two stage filter is a compensating 21 tap decimate by 2 filter (CFIR) with a choice of two sets of fixed tap weights. The first set is designed to be flat from -0.5FS to +0.5FS, where FS is the output sample rate, and to reject out of band energy by at least 80dB. The second set has a narrower output passband (-0.25FS to +0.25FS), but more out of band rejection. The second set is ideal for systems such as GSM, which require more far band rejection (>97 dB), but with relaxed adjacent band rejection. The second stage is a 63 tap decimate by 2 or 4 programmable filter (PFIR) with either internal or user supplied tap weights. The internal filter is designed to be flat from -0.4FS to +0.4FS of the output sample rate and to reject out of band energy by at least 85 dB. The user can also design and download their own final filter to customize the channel’s spectral response. Typical uses of the programmable filter include matched (root-raised cosine) filtering, or filtering to generate oversampled outputs with greater out of band rejection. The 63 tap symmetrical filter is downloaded into the chip as 32 words, 16 bits each. The programmable PFIR coefficients must be used to bandlimit the output in the decimate by 4 mode. 1. Hogenauer, Eugene B., An Economical Class of Digital Filters for Decimation and Interpolation, IEEE transactions on Acoustics, Speech and Signal Processing, April 1981. NCO TUNING FREQUENCY PHASE OFFSET IN TO OUTPUT FORMATTER Q I |
Nº de peça semelhante - SLWS132 |
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Descrição semelhante - SLWS132 |
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