SN54AS194, SN74AS194

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994

2

POST OFFICE BOX 655303

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

MODE

CLK

SERIAL

PARALLEL

QA

QB

QC

QD

CLR

S1

S0

CLK

LEFT

RIGHT

A

B

C

D

QA

QB

QC

QD

L

X

X

X

X

X

X

X

X

X

L

L

L

L

H

X

XL

X

XX

XX

X

QA0

QB0

QC0

QD0

H

H

H

↑

X

Xa

bc

d

a

bc

d

H

L

H

↑

X

HX

XX

X

H

QAn

QBn

QCn

H

L

H

↑

X

LX

XX

X

L

QAn

QBn

QCn

H

H

L

↑

H

XX

XX

X

QBn

QCn

QDn

H

H

H

L

↑

L

XX

XX

X

QBn

QCn

QDn

L

H

L

L

X

X

X

X

X

X

X

QA0

QB0

QC0

QD0

H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions);

↑ = transition from

low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; QA0, QB0, QC0, QD0 = the

levelof QA,QB,QC,orQD,respectively,beforetheindicatedsteady-stateinputconditionswereestablished;QAn,QBn,QCn,

QDn = the level of QA, QB, QC, respectively, before the most recent ↑ transition of the clock.

SRG4

3, 4D

4

B

3, 4D

5

C

3, 4D

6

D

2, 4D

7

SL SER

1, 4D

2

SR SER

3, 4D

3

A

R

1

11

CLK

C4

M

0

3

14

13

15

1

10

S1

0

9

S0

1

/2

12

CLR

QA

QB

QC

QD

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.