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SN74ABT3614-30PCB Folha de dados(PDF) 10 Page - Texas Instruments |
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SN74ABT3614-30PCB Folha de dados(HTML) 10 Page - Texas Instruments |
10 / 41 page SN74ABT3614 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SCBS126H – JUNE 1992 – REVISED APRIL 2000 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 almost-full flags (AFA, AFB) The FIFO almost-full flag is synchronized to the port clock that writes data to its array. The almost-full state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset ). An almost-full flag is low when the FIFO contains (64 – X) or more long words in memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words. Two low-to-high transitions of the AF-flag synchronizing clock are required after a FIFO read for the AF flag to reflect the new level of fill; therefore, the AF flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64 – (X + 1)]. An AF flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to [64 – (X + 1)]. A low-to-high transition of an AF-flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words in memory to [64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 19 and 20). mailbox registers Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0 and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low. When the port-A data outputs (A0 – A35) are active, the data on the bus comes from the FIFO2 output register when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0 – B35) are active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both SIZ1 and SIZ0 are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only when new data is written to the register. dynamic bus sizing The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths. The levels applied to the port-B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to Figure 1. Only 36-bit long-word data is written to or read from the two FIFO memories on the SN74ABT3614. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. Port-B bus sizing does not apply to mail-register operations. |
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