SN74ALVCH16820

3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS

AND 3-STATE OUTPUTS

SCES035E – JULY 1995 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303

Widebus

™ Family

CMOS) Submicron Process

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Need for External Pullup/Pulldown

Resistors

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 10-bit flip-flop is designed for 1.65-V to 3.6-V

The flip-flops of the SN74ALVCH16820 are

edge-triggered D-type flip-flops. On the positive

transition of the clock (CLK) input, the device

provides true data at the Q outputs.

A buffered output-enable (OE) input can be used

to place the ten outputs in either a normal logic

state

(high

or

low

logic

level)

or

the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without need for interface or pullup

components.

OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be

entered while the outputs are in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16820 is characterized for operation from –40

°C to 85°C.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG OR DL PACKAGE

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1OE

1Q1

1Q2

GND

2Q1

2Q2

3Q1

3Q2

4Q1

GND

4Q2

5Q1

5Q2

6Q1

6Q2

7Q1

GND

7Q2

8Q1

8Q2

9Q1

9Q2

GND

10Q1

10Q2

2OE

CLK

D1

NC

GND

D2

NC

D3

NC

D4

GND

NC

D5

NC

D6

NC

D7

GND

NC

D8

NC

D9

NC

GND

D10

NC

NC

NC – No internal connection

EPIC and Widebus are trademarks of Texas Instruments Incorporated.