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SN74CBTLV3861DGV Folha de dados(PDF) 4 Page - Texas Instruments |
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SN74CBTLV3861DGV Folha de dados(HTML) 4 Page - Texas Instruments |
4 / 6 page SN74CBTLV3861 LOW-VOLTAGE 10-BIT FET BUS SWITCH SCDS041D – DECEMBER 1997 – REVISED NOVEMBER 1999 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V VCC/2 VCC/2 VCC/2 VCC/2 VOH VOL From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 Ω 500 Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH – 0.15 V 0 V VCC VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. tPHL VCC/2 VCC/2 VCC 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VCC/2 tPLH 2 × VCC VCC Figure 1. Load Circuit and Voltage Waveforms |
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