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TL16C550AFN Folha de dados(PDF) 4 Page - Texas Instruments

Nome de Peças TL16C550AFN
Descrição Electrónicos  ASYNCHRONOUS COMMUNICATIONS ELEMENT
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.†
I/O
DESCRIPTION
A0
A1
A2
28 [31]
27 [30]
26 [29]
I
Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description.
ADS
25 [28]
I
Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0,
CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in
the state they were in when the low-to-high transition of ADS occurred.
BAUDOUT
15 [17]
O
Baud out. BAUDOUT is a 16
× clock signal for the transmitter section of the ACE. The clock rate is established by
the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.
CS0
CS1
CS2
12 [14]
13 [15]
14 [16]
I
Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description.
CTS
36 [40]
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.
D0 – D7
1 – 8
[2 – 9]
I/O
Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the
ACE and the CPU.
DCD
38 [42]
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes
state, an interrupt is generated.
DDIS
23 [26]
O
Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable
an external transceiver.
DSR
37 [41]
I
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.
DTR
33 [37]
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level.
DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing
bit 0 (DTR) of the modem control register.
INTRPT
30 [33]
O
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.
MR
35 [39]
I
Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer
to Table 2.
OUT1
OUT2
34 [38]
31 [35]
O
Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.
RCLK
9 [10]
I
Receiver clock. RCLK is the 16
× baud rate clock for the receiver section of the ACE.
RD1
RD2
21 [24]
22 [25]
I
Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1 tied high).
† Terminal numbers shown in brackets are for the FN package.


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