TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

NAME

NO.

FN

NO.

PM

I/O

DESCRIPTION

A0

A1

A2

31

30

29

20

18

17

I

Register select. A0 – A2 are used during read and write operations to select the ACE register to read from

or write to. Refer to Table 1 for register addresses and ADS signal description.

ADS

28

15

I

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals

(CS0, CS1, CS2) drive the internal select logic directly; when ADS is high, the register select and chip select

signals are held at the logic levels they were in when the low-to-high transition of ADS occurred.

BAUDOUT

17

64

O

Baud out. BAUDOUT is a 16

× clock signal for the transmitter section of the ACE. The clock rate is established

by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.

BAUDOUT can also be used for the receiver section by tying this output to RCLK.

CS0

CS1

CS2

14

15

16

59

61

62

I

Chip select. When CS0 and CS1 are high and CS2 is low, the ACE is selected. When any of these inputs

are inactive, the ACE remains inactive. Refer to the ADS signal description.

CTS

40

33

I

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the

modem status register. Bit 0 (

∆CTS) of the modem status register indicates that CTS has changed states

since the last read from the modem status register. When the modem status interrupt is enabled, CTS

changes states, and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the

auto-CTS mode to control the transmitter.

D0

D1

D2

D3

D4

D5

D6

D7

2

3

4

5

6

7

8

9

42

43

45

46

48

50

51

52

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU. As inputs, they use fail safe CMOS compatible input buffers.

DCD

42

36

I

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of

the modem status register. Bit 3 (

∆DCD) of the modem status register indicates that DCD has changed states

since the last read from the modem status register. When the modem status interrupt is enabled and DCD

changes state, an interrupt is generated.

DDIS

26

12

O

Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an

external transceiver.

DSR

41

35

I

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the

modem status register. Bit 1 (

∆DSR) of the modem status register indicates DSR has changed states since

the last read from the modem status register. When the modem status interrupt is enabled and the DSR

changes states, an interrupt is generated.

DTR

37

28

O

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish

communication. DTR is placed in the active state by setting the DTR bit of the modem control register to one.

DTR is placed in the inactive condition either as a result of a master reset, during loop mode operation, or

clearing the DTR bit.

INTRPT

33

23

O

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed

out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT

is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

MR

39

32

I

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals

(refer to Table 2).

OUT1

OUT2

38

35

30

25

O

Outputs 1 and 2. These are user-designated output terminals that are set to their active (low) level by setting

their respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to their

inactive (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or

bit 3 (OUT2) of the MCR.

RCLK

10

54

I

Receiver clock. RCLK is the 16

× baud rate clock for the receiver section of the ACE.