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TSB12LV22 Folha de dados(PDF) 8 Page - Texas Instruments

Nome de Peças TSB12LV22
Descrição Electrónicos  OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
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TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
vendor ID register
This 16-bit read only register contains a value allocated by the PCI SIG and identifies the manufacturer of the
PCI device. The Vendor ID assigned to Texas Instruments is 104Ch. All bits in this register are read only.
PCI register 00h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset State
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
device ID register
This 16-bit read only register contains a value assigned to the OHCI-Lynx by Texas Instruments. The device
identification for the OHCI-Lynx is 8009.
PCI register 02h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset State
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
PCI command register
The command register provides control over the OHCI-Lynx interface to the PCI bus. All bit functions adhere
to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions.
PCI register 04h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4. Bit Descriptions – PCI Command Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
9
FBB_ENB
r
Fast Back-to-Back Enable. The OHCI-Lynx will not generate fast back to back transactions, thus this bit
is read only and returns zero when read.
8
SERR_ENB
rw
SERR# Enable. When set, the OHCI-Lynx SERR# driver is enabled. SERR# can be asserted after de-
tecting an address parity error on the PCI bus.
7
STEP_ENB
r
Address/Data Stepping Control. The OHCI-Lynx does not support address/data stepping, and this bit is
hardwired to zero.
6
PERR_ENB
rw
Parity Error Enable. When set, the OHCI-Lynx is enabled to drive PERR# response to parity errors
through the PERR# signal.
5
VGA_ENB
r
VGA Palette Snoop Enable. The OHCI-Lynx does not feature VGA palette snooping, and this bit is read
only returning zeros when read.
4
MWI_ENB
rw
Memory Write and Invalidate Enable. When set, the OHCI-Lynx is enabled to generate MWI pci bus
commands. If reset, the OHCI-Lynx will generate memory write commands instead.
3
SPECIAL
r
Special Cycle Enable. The OHCI-Lynx function does not respond to special cycle transactions, and this
bit is read only and returns zero when read.
2
MASTER_ENB
rw
Bus Master Enable. When set, the OHCI-Lynx is enabled to initiate cycles on the PCI bus.
1
MEMORY_ENB
rw
Memory Response Enable. Setting this bit enables the OHCI-Lynx to respond to memory cycles on the
PCI bus. This bit must be set to access OHCI registers.
0
IO_ENB
r
I/O Space Enable. The OHCI-Lynx does not implement any I/O mapped functionality; thus, this bit is
read only and returns zeros when read.


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