CDCE62002RHBR datasheet(1/49 Pages) TI

Nome de Peças	CDCE62002RHBR

Descrição Electrónicos	Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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Fabricante Electrônico	TI [Texas Instruments]

Página de início	http://www.ti.com

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FEATURES

APPLICATIONS

CDCE62002

www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009

Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

• Flexible Inputs With Innovative Smart

Multiplexer Feature:

• Frequency Synthesizer With PLL/VCO and

Partially Integrated Loop Filter

–

Two Universal Differential Inputs Accept

Frequencies from 1 MHz up to 500 MHz

• Fully Configurable Outputs Including

(LVPECL), 500 MHz (LVDS), or 250 MHz

Frequency and Output Format

(LVCMOS).

• Smart Input Multiplexer Automatically

–

One Auxiliary Input Accepts Single Ended

Switches Between one of two Reference

Clock Source or Crystal. Auxiliary Input

Inputs.

Accepts Crystals in the Range of

• Multiple Operational Modes Include Clock

2MHz–42MHz or an LVCMOS Input up to

Generation via Crystal, SERDES Startup Mode,

75MHz.

Jitter Cleaning, and Oscillator Based Holdover

–

Clock Generator Mode Using Crystal Input

Mode.

–

Smart Input Multiplexer can be Configured

• Integrated EEPROM Determines Device

to Automatically Switch Between Highest

Configuration at Power-up.

Priority Clock Source Available Allowing

• Excellent Jitter Performance

for Fail-Safe Operation.

• Integrated Frequency Synthesizer Including

• Typical Power Consumption 750mW at 3.3V

PLL, Multiple VCOs, and Loop Filter:

• Integrated EEPROM Stores Default Settings;

–

Full Programmability Facilitates Phase

Therefore, the Device can Power up in a

Noise Performance Optimization Enabling

Known, Predefined State.

Jitter Cleaner Mode

• Offered in QFN-32 Package

–

Programmable Charge Pump Gain and

• ESD Protection Exceeds 2kV HBM

Loop Filter Settings

• Industrial Temperature Range –40°C to 85°C

–

Unique Dual-VCO Architecture Supports a

Wide Tuning Range 1.750 GHz – 2.356 GHz.

• Universal Output Blocks Support up to 2

• Data Converter and Data Aggregation Clocking

Differential, 4 Single-Ended, or Combinations

• Wireless Infrastructure

of Differential or Single-Ended:

• Switches and Routers

–

0.5 ps RMS (10 kHz to 20 MHz) Output

• Medical Electronics

Jitter Performance

• Military and Aerospace

–

Low Output Phase Noise: –130 dBc/Hz

• Industrial

at 1 MHz offset, Fc = 491.52 MHz

• Clock Generation and Jitter Cleaning

–

Output Frequency Ranges From 10.94

MHz to 1.175 GHz in Synthesizer Mode

–

LVPECL, LVDS and LVCMOS

–

Independent Output Dividers Support

Divide Ratios for

1,2,3,4,5,8,10,12,16,20,24 and 32.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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