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TSB41LV06APZP Folha de dados(PDF) 10 Page - Texas Instruments |
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TSB41LV06APZP Folha de dados(HTML) 10 Page - Texas Instruments |
10 / 48 page TSB41LV06A IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER SLLS363 – SEPTEMBER1999 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DISSIPATION RATING TABLE PACKAGE TA ≤ 25_C POWER RATING DERATING FACTOR† ABOVE TA = 25_C TA = 70_C POWER RATING PZP‡ 4.48 W 44.78 mW/ °C 2.46 W PZP§ 2.28 W 22.78 mW/ °C 1.25 W PZP¶ 1.32 W 13.19 mW/ °C 0.73 W † This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). ‡ 1 oz. trace and copper pad with solder. § 1 oz. trace and copper pad without solder. ¶ Standard JEDEC High-K board NOTE: For more information, refer to TI application note PowerPAD Thermally Enhanced Package TI literature number SLMA002. recommended operating conditions PARAMETER MIN TYP† MAX UNIT Supply voltage VDD Source power node 3 3.3 3.6 V Supply voltage, VDD Nonsource power node 2.7‡ 3 3.6 High-level input voltage, VIH Case 1 (bus holder): ISO=VDD, VDD_5V = VDD Case 2 (5V Tol): ISO=VDD, VDD_5V = 5V LREQ, CTL0, CTL1, D0–D7 2.6 V High level in ut voltage, VIH C/LKON, PC0, PC1, PC2, ISO, PD 0.7 ×VDD V RESET 0.6 ×VDD V Low-level input voltage, VIL Case 1 (bus holder): ISO=VDD, VDD_5V = VDD Case 2 (5V Tol): ISO=VDD, VDD_5V = 5 V LREQ, CTL0, CTL1, D0–D7 1.2 V Low level in ut voltage, VIL C/LKON, PC0, PC1, PC2, ISO, PD 0.2 ×VDD V RESET 0.3 ×VDD V Output current, IO TPBIAS outputs –5.6 1.3 mA Maximum junction temperature TJ (see R θJA= 17.85°C/W, TA=70°C 93.6 Maximum junction tem erature TJ (see R θJA values listed in thermal R θJA =28.22°C/W, TA=70°C 107.3 °C characteristics table) R θJA =49.17°C/W, TA=70°C 135.1 Differential input voltage VID Cable inputs, during data reception 118 260 mV Differential input voltage, VID Cable inputs, during arbitration 168 265 mV Common mode input voltage VIC TPB cable inputs, Source power node 0.4706 2.515 V Common-mode input voltage, VIC TPB cable inputs, Nonsource power node 0.4706 2.015‡ V Power-up reset time, tpu RESET input 2 ms TPA, TPB cable inputs, S100 operation ±1.08 Receive input jitter TPA, TPB cable inputs, S200 operation ±0.5 ns TPA, TPB cable inputs, S400 operation ±0.315 Between TPA and TPB cable inputs, S100 operation ±0.8 Receive input skew Between TPA and TPB cable inputs, S200 operation ±0.55 ns Between TPA and TPB cable inputs, S400 operation ±0.5 † All typical values are at VDD = 3.3 V and TA = 25°C. ‡ For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a. |
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