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ISL24021IRT065Z-T13 Folha de dados(PDF) 11 Page - Intersil Corporation |
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ISL24021IRT065Z-T13 Folha de dados(HTML) 11 Page - Intersil Corporation |
11 / 12 page 11 FN6637.0 June 3, 2009 Printed Circuit Board Layout As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. For the ISL24021 low impedance analog power and ground planes are recommended, and trace lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. For optimal thermal and operating performance the ISL24021 thermal pad should always be connected to the lowest potential, VSS. For normal single supply operation (the VSS pin is connected to GND) a 4.7µF capacitor should be placed from VDD to GND, then a parallel 0.1µF capacitor should be connected as close to the amplifier as possible. For dual supply operation the same bypassing techniques should be utilized by connecting capacitors from each supply to GND. FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD - TDFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 25 50 75 100 125 150 AMBIENT TEMP (°C) θJA = +50 (°C/W) 2.5W TDFN8 ISL24021 |
Nº de peça semelhante - ISL24021IRT065Z-T13 |
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Descrição semelhante - ISL24021IRT065Z-T13 |
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