4

FN6690.1

September 26, 2008

SCL Frequency

400

kHz

Pulse width Suppression Time at SDA and

SCL Inputs

Any pulse narrower than the max

spec is suppressed.

50

ns

SCL Falling Edge to SDA Output Data Valid

SCL falling edge crossing 30% of

900

ns

Time the Bus Must be Free Before the Start

of a New Transmission

a STOP condition, to SDA

following START condition.

1300

ns

Clock LOW Time

crossing.

1300

ns

Clock HIGH Time

crossing.

600

ns

START Condition Setup Time

SCL rising edge to SDA falling

600

ns

START Condition Hold Time

From SDA falling edge crossing

600

ns

Input Data Setup Time

From SDA exiting the 30% to 70%

100

ns

Input Data Hold Time

From SCL falling edge crossing

20

900

ns

STOP Condition Setup Time

From SCL rising edge crossing

600

ns

STOP Condition Hold Time

From SDA rising edge to SCL

falling edge. Both crossing 70% of

600

ns

Output Data Hold Time

From SCL falling edge crossing

0ns

SDA and SCL Rise Time

20 +

0.1 x Cb

300

ns

6, 7

SDA and SCL Fall Time

20 +

0.1 x Cb

300

ns

6, 7

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

6, 7

Rpu

For Cb = 400pF, max is about

2k

Ω to~2.5kΩ.

For Cb = 40pF, max is about 15k

Ω

to ~20k

Ω.

1k

Ω

6, 7

NOTES:

2. FT/OUT inactive.

3. LPMODE = 0 (default).

5. Typical values are for T = +25°C and 3.3V supply voltage.

6. Limits should be considered typical and are not production tested.

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

Serial Interface Specifications

Recommended Operating Conditions. Unless otherwise specified. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 8)

TYP

(Note 5)

MAX

(Note 8)

UNITS NOTES

ISL12008