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STK14C88-5
Document Number: 001-51038 Rev. **
Page 9 of 17
AC Switching Characteristics
SRAM Read Cycle
Parameter
Description
35 ns
45 ns
Unit
Min
Max
Min
Max
Cypress
Parameter
Alt
tACE
tELQV
Chip Enable Access Time
35
45
ns
tRC
[9]
tAVAV, tELEH
Read Cycle Time
35
45
ns
tAA
[10]
tAVQV
Address Access Time
35
45
ns
tDOE
tGLQV
Output Enable to Data Valid
15
20
ns
tOHA
[10]
tAXQX
Output Hold After Address Change
5
5
ns
tLZCE
[11]
tELQX
Chip Enable to Output Active
5
5
ns
tHZCE
[11]
tEHQZ
Chip Disable to Output Inactive
13
15
ns
tLZOE
[11]
tGLQX
Output Enable to Output Active
0
0
ns
tHZOE
[11]
tGHQZ
Output Disable to Output Inactive
13
15
ns
tPU
[8]
tELICCH
Chip Enable to Power Active
0
0
ns
tPD
[8]
tEHICCL
Chip Disable to Power Standby
35
45
ns
Switching Waveforms
Figure 8. SRAM Read Cycle 1: Address Controlled [9, 10]
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [9]
Notes
9. WE and HSB must be HIGH during SRAM Read cycles.
10. Device is continuously selected with CE and OE both Low.
11. Measured ±200 mV from steady state output voltage.
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