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STK16C88
Document Number: 001-50595 Rev. **
Page 8 of 14
AC Switching Characteristics
Table 3. SRAM Read Cycle
Parameter
Description
25 ns
45 ns
Unit
Min
Max
Min
Max
Cypress
Parameter
Alt
tACE
tELQV
Chip Enable Access Time
25
45
ns
tRC
[5]
tAVAV, tELEH
Read Cycle Time
25
45
ns
tAA
[6]
tAVQV
Address Access Time
25
45
ns
tDOE
tGLQV
Output Enable to Data Valid
10
20
ns
tOHA
[6]
tAXQX
Output Hold After Address Change
5
5
ns
tLZCE
[7]
tELQX
Chip Enable to Output Active
5
5
ns
tHZCE
[7]
tEHQZ
Chip Disable to Output Inactive
10
15
ns
tLZOE
[7]
tGLQX
Output Enable to Output Active
0
0
ns
tHZOE
[7]
tGHQZ
Output Disable to Output Inactive
10
15
ns
tPU
[4]
tELICCH
Chip Enable to Power Active
0
0
ns
tPD
[4]
tEHICCL
Chip Disable to Power Standby
25
45
ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 6]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]
Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
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