5 / 16 page
STK14CA8
Document Number: 001-51592 Rev. **
Page 5 of 16
SRAM READ Cycles #1 and #2
Figure 6. SRAM READ Cycle #1: Address Controlled[3, 4, 6]
Figure 7. SRAM READ Cycle #2: E and G Controlled[3, 6]
NO.
Symbols
Parameter
STK14CA8-25 STK14CA8-35 STK14CA8-45
Units
#1
#2
Alt.
Min
Max
Min
Max
Min
Max
1
tELQV
tACS
Chip Enable Access Time
25
35
45
ns
2
tAVAV
[3]
tELEH
[3]
tRC
Read Cycle Time
25
35
45
ns
3
tAVQV
[4]
tAVQV
[4]
tAA
Address Access Time
25
35
45
ns
4
tGLQV
tOE
Output Enable to Data Valid
12
15
20
ns
5
tAXQX
[4]
tAXQX
[4]
tOH
Output Hold after Address Change
3
3
3
ns
6
tELQX
tLZ
Address Change or Chip Enable to
Output Active
33
3
ns
7
tEHQZ
[5]
tHZ
Address Change or Chip Disable to
Output Inactive
10
13
15
ns
8
tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9
tGHQZ
[5]
tOHZ
Output Disable to Output Inactive
10
13
15
ns
10
tELICCH
[2]
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCL
[2]
tPS
Chip Disable to Power Standby
25
35
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured
± 200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles
2
29
11
7
9
10
8
4
3
6
1
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