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UC1825A Folha de dados(PDF) 6 Page - Texas Instruments |
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UC1825A Folha de dados(HTML) 6 Page - Texas Instruments |
6 / 9 page 6 UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B UVLO, SOFT START AND FAULT MANAGEMENT Soft start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amp output is also forced low. As the internal 9 µA source charges the SS pin, the error amp output follows until closed loop regulation takes over. Anytime ILIM exceeds 1.2V, the fault latch will be set and the output pins will be driven low. The soft start cap is then discharged by a 250 µA current sink. No more output pulses are allowed until soft start is fully discharged, and ILIM is below 1.2V. At this point the fault latch will be re- set and the chip will execute a soft start. Should the fault latch be set during soft start, the outputs will be immediately terminated, but the soft start cap will not be discharged until it has been fully charged. This re- sults in a controlled hiccup interval for continuous fault conditions. APPLICATIONS INFORMATION (cont.) PWM APPLICATIONS ACTIVE LOW OUTPUTS DURING UVLO The UVLO function forces the outputs to be low and con- siders both VCC and VREF before allowing the chip to operate. Output V and I During UVLO Simplified Schematic Current Mode Voltage Mode Soft Start and Fault Waveforms UDG-95107 UDG-95108 UDG-95110 UDG-95109 UDG-95106 |
Nº de peça semelhante - UC1825A |
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Descrição semelhante - UC1825A |
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