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CS8422 Folha de dados(PDF) 11 Page - Cirrus Logic

Nome de Peças CS8422
Descrição Electrónicos  24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver
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Fabricante Electrônico  CIRRUS [Cirrus Logic]
Página de início  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8422 Folha de dados(HTML) 11 Page - Cirrus Logic

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DS692PP2
11
CS8422
1.2
Hardware Mode
Pin Name
Pin #
Pin Description
RXP/RXN[1:0]
1
2
5
6
AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital
data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0]
comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND.
VA
3
Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that
this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of
the recovered clock.
AGND
4
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
SAOF
7
Serial Audio Output Format Select (Input) - Used to select the serial audio output format after
reset. See Table 4 on page 41 for format settings.
MS_SEL
8
Master/Slave Select (Input) - Used to select Master or Slave settings for the input and output serial
audio ports after reset. See Table 5 on page 41 for format settings.
NV/RERR
9
Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by
default, RERR is selected by a 20 k
Ω resistor to VL.
V/AUDIO
10
Validity Data/AUDIO (Output) - If a 20 k
Ω pull-down is present on this pin, it will output serial Validity
data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a
20 k
Ω pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input.
XTI
11
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock”
on page 38.
XTO
12
Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38.
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Top-Down View
32-Pin QFN Package
Thermal Pad
OSCLK2
VA
AGND
SAOF
RXP0
SDOUT2
VL
RXN0
RXP1
RXN1
TX/U
VD_FILT
V_REG
MS_SEL
C
DGND


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