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ISL35111 Folha de dados(PDF) 6 Page - Intersil Corporation

Nome de Peças ISL35111
Descrição Electrónicos  11.1Gb/s Driver
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL35111 Folha de dados(HTML) 6 Page - Intersil Corporation

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FN6975.0
November 19, 2009
CML Input and Output Buffers
The input and output buffers for the high-speed data
channel in the ISL35111 are implemented using CML.
Equivalent input and output circuits are shown in
Figures 6 and 7.
Adjustable De-Emphasis
ISL35111 features a settable de-emphasis driver for
custom signal restoration.
The connectivity of the DE pins are used to determine the
boost de-emphasis level of ISL35111. Table 1 defines the
mapping from the 2-bit non-binary DE word to the 7
available output de-emphasis levels.
Disable Pin
The disable (TDSBL) pin is used to disable the driver
output in order to implement TX_Disable functions of
such industry standards as SFP+ and QSFP. When this
pin is pulled HIGH, the ISL35111 will enter a low-power
standby mode. For active data transmission, this pin
must be pulled LOW.
Line Silence/Quiescent Mode
The ISL35111 is capable of maintaining periods of line
silence by monitoring its input pins for loss of signal
(LOS) conditions and subsequently muting the output
driver when such a condition is detected. A reference
voltage applied to the detection threshold (DT) pin is
used to set the LOS threshold of the internal signal
detection circuitry. For most applications, it is
recommended to leave the DT pin floating at its default
internal bias. If the sensitivity of the detection threshold
needs to be adjusted, the DT voltage can be adjusted
with an external pull-up resistor. The resistor values
should be validated on an application-specific basis.
Connect the DT pin to ground in order to disable this
feature and prevent the outputs from muting during line
silence.
About Q:ACTIVE®
Intersil has long realized that to enable the complex
server clusters of next generation datacenters, it is
critical to manage the signal integrity issues of electrical
interconnects. To address this, Intersil has developed its
groundbreaking Q:ACTIVE® product line. By integrating
its analog ICs inside cabling interconnects, Intersil is able
to achieve unsurpassed improvements in reach, power
consumption, latency, and cable gauge size as well as
increased airflow in tomorrow's datacenters. This new
technology transforms passive cabling into intelligent
"roadways" that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing
cabling while reducing the need for thicker cables. This
significantly reduces cable weight and clutter, increases
airflow, and improves power consumption.
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR THE
ISL35111
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE ISL35111
IN[P]
IN[N]
1
st LA
Stage
VDD
50O
50O
2kO
10kO
Ω
Ω
Ω
Ω
VDD
50O
50O
OUT[P]
OUT[N]
Ω
Ω
TABLE 1. MAPPING BETWEEN DE-EMPHASIS LEVEL
AND DE-PIN CONNECTIVITY
DE PIN
CONNECTION
NOMINAL
DE-EMPHASIS LEVEL;
10.3125Gbps TO
11.1Gbps (dB)
DE-EMPHASIS
SETTING
DE[A]
DE[B]
Open
Open
0
0
Open
GND
0.6
1
Open
VDD
1.1
2
GND
Open
1.6
3
GND
GND
2.3
4
GND
VDD
3
5
VDD
Open
4
6
ISL35111


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