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ADE5569ASTZF62 Folha de dados(PDF) 10 Page - Analog Devices

Nome de Peças ADE5569ASTZF62
Descrição Electrónicos  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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ADE5166/ADE5169/ADE5566/ADE5569
Rev. B | Page 10 of 156
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and at VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when
a 100 mV change from load voltage occurs. A port pin begins
to float when a 100 mV change from the loaded VOH/VOL level
occurs, as shown in Figure 3.
CLOAD = 80 pF for all outputs, unless otherwise noted. VDD = 2.7 V
to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
VSWOUT – 0.5V
0.45V
0.2VSWOUT + 0.9V
TEST POINTS
0.2VSWOUT – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameters
32.768 kHz External Crystal
Parameter
Description
Min
Typ
Max
Unit
tCK
XTAL1 period
30.52
μs
tCKL
XTAL1 width low
6.26
μs
tCKH
XTAL1 width high
6.26
μs
tCKR
XTAL1 rise time
9
ns
tCKF
XTAL1 fall time
9
ns
1/tCORE
Core clock frequency1
1.024
MHz
1 The ADE5166/ADE5169/ADE5566/ADE5569 internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal
clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter
Description
Typ
Unit
tBUF
Bus-free time between stop condition and start condition
1.3
μs
tL
SCLK low pulse width
1.36
μs
tH
SCLK high pulse width
1.14
μs
tSHD
Start condition hold time
251.35
μs
tDSU
Data setup time
740
ns
tDHD
Data hold time
400
ns
tRSU
Setup time for repeated start
12.5
ns
tPSU
Stop condition setup time
400
ns
tR
Rise time of both SCLK and SDATA
200
ns
tF
Fall time of both SCLK and SDATA
300
ns
tSUP1
Pulse width of spike suppressed
50
ns
1 Input filtering on both the SCLK and SDATA suppresses noise spikes of <50 ns.
MSB
tBUF
SDATA (I/O)
SCLK (I)
STOP
CONDITION
START
CONDITION
REPEATED
START
LSB
ACK
MSB
1
2TO 7
89
1
S(R)
PS
tPSU
tDSU
tSHD
tDHD
tDSU
tDHD
tSUP
tH
tSUP
tL
tRSU
tR
tR
tF
tF
Figure 4. I2C-Compatible Interface Timing


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