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ST7573 Folha de dados(PDF) 10 Page - Sitronix Technology Co., Ltd. |
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ST7573 Folha de dados(HTML) 10 Page - Sitronix Technology Co., Ltd. |
10 / 46 page ST7573 Ver 1.0b 10/46 2007/07/12 VGI, VGO, VGS Power LCD driving voltage for segments. VGI is the VG power source for the LCD driver. If using external VG, apply external power source on these pads. VGO is the internal VG regulator output pad. VGS is the feedback for the internal VG voltage compensation circuit. They should be separate in ITO and be connected together by FPC. 7 VM Power LCD driving voltage for commons. 3 CONFIGURATION PIN MLB I Data format (MSB on top or LSB on top). MLB=”H”, MSB on top (D7 on top); MLB=”L”, LSB on top (D0 on top). 1 PM I Set power mode. This pin will change the V0 (Vop) formula parameter. V0=( a + VOP[6:0] x b ) PM=”L”, a=3.0V, b=0.03V; PM=”H”, a=4.5V, b=0.03V. 1 TEST PIN T0…T11 Test T0~T8: left them open. T9 must connect to VSS. T10 and T11 must connect to VDD. 12 The unused pins should be left floating. The Microprocessor Interface pins should not be left floating under any operation mode. Recommend I/O pins ITO Resistance Limitation Pin Name ITO Resistance VRS, T[8:0] Floating VSS <100Ω Ω Ω Ω VDD <100Ω Ω Ω Ω VDD2 <100Ω Ω Ω Ω V0 (V0I + V0O + V0S), XV0 (XV0I + XV0O + XV0S), VG (VGI + VGO + VGS), VM <500Ω Ω Ω Ω CSB, A0, /RD, /WR, D[7:0] <1KΩ Ω Ω Ω PS[2:0], OSC *1, MLB, T[11:9] <5KΩ Ω Ω Ω RESB <10KΩ Ω Ω Ω Notes: 1. If using internal clock, OSC is connect to VDD and the limitation of ITO resistance will be “No Limitation”. If using external clock, the ITO resistance of OSC should be kept lower than 500 to keep the clock signal quality. |
Nº de peça semelhante - ST7573 |
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Descrição semelhante - ST7573 |
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