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DM9000AE Folha de dados(PDF) 11 Page - Davicom Semiconductor, Inc. |
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DM9000AE Folha de dados(HTML) 11 Page - Davicom Semiconductor, Inc. |
11 / 60 page DM9000A Ethernet Controller with General Processor Interface Final 11 Version: DM9000A-17-DS-F01 May 10, 2006 These pins are input ports at default. 5.2 EEPROM Interface Pin No. Pin Name Type Description 19 EEDIO I/O,PD IO Data to EEPROM 20 EECK O,PD Clock to EEPROM This pin is also used as the strap pin of the polarity of the INT pin When this pin is pulled high, the INT pin is low active; otherwise the INT pin is high active 21 EECS O,PD Chip Select to EEPROM This pin is also used as a strap pin to define the internal memory data bus width. When it is pulled high, the memory access bus is 8-bit; Otherwise it is 16-bit. 5.3 Clock Interface Pin No. Pin Name Type Description 43 X2 O Crystal 25MHz Out 44 X1 I Crystal 25MHz In 5.4 LED Interface Pin No. Pin Name Type Description 39 LED1 O Speed LED Its low output indicates that the internal PHY is operated in 100M/S, or it is floating for the 10M mode of the internal PHY. This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit mode. 38 LED2 O Link / Active LED In LED mode 1, it is the combined LED of link and carrier sense signal of the internal PHY In LED mode 0, it is the LED of the carrier sense signal of the internal PHY only This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM setting in 16-bit mode. 5.5 10/100 PHY/Fiber Pin No. Pin Name Type Description 46 SD I Fiber-optic Signal Detect PECL signal, which indicates whether or not the fiber-optic receive pair is receiving valid levels 48 BGGND P Bandgap Ground 1 BGRES I/O Bandgap Pin 2 RXVDD25 P 2.5V power output for TP RX 9 TXVDD25 P 2.5V power output for TP TX 3 RX+ I/O TP RX Input |
Nº de peça semelhante - DM9000AE |
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Descrição semelhante - DM9000AE |
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