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74AUP1G0832GW Folha de dados(PDF) 1 Page - NXP Semiconductors

Nome de Peças 74AUP1G0832GW
Descrição Electrónicos  Low-power 3-input AND-OR gate
Download  16 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1G0832GW Folha de dados(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74AUP1G0832 provides the Boolean function: Y = (A
× B) + C. The user can choose
the logic functions OR, AND and AND-OR. All inputs can be connected to VCC or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °Cto+85 °C and −40 °C to +125 °C
74AUP1G0832
Low-power 3-input AND-OR gate
Rev. 02 — 3 July 2009
Product data sheet


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