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74AUP2T1326GF Folha de dados(PDF) 10 Page - NXP Semiconductors |
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74AUP2T1326GF Folha de dados(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 74AUP2T1326_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 1 July 2009 10 of 16 NXP Semiconductors 74AUP2T1326 Low-power dual supply buffer/line driver; 3-state [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. [1] VCCI is the supply voltage associated with the data input port. [2] For measuring enable and disable times, CL and RL are connected to pin 2Y and 3Y. [3] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays RL =1MΩ. [4] VCCO is the supply voltage associated with the output port. Table 9. Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH − 0.15 V Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 5. Test circuit for measuring switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Input Load[2] VEXT VCC(A), VCC(B) VI[1] tr = tf CL RL[3] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[4] 1.65 V to 2.7 V VCCI ≤ 3.0 ns 5 pF, 10 pF 5 k Ω or 1 MΩ open GND 2VCCO |
Nº de peça semelhante - 74AUP2T1326GF |
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Descrição semelhante - 74AUP2T1326GF |
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