DM355SZCEA135 datasheet(1/159 Pages) TI

Nome de Peças	DM355SZCEA135

Descrição Electrónicos	Digital Media System-on-Chip (DMSoC)

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Fabricante Electrônico	TI [Texas Instruments]

Página de início	http://www.ti.com

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TMS320DM355 Digital Media System-on-Chip (DMSoC)

1.1 Features

TMS320DM355

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS463F – SEPTEMBER 2007 – REVISED JANUARY 2009

• 8-/16-bit YCC and Up to 18-Bit RGB666

• High-Performance Digital Media

Digital Output

System-on-Chip

• BT.601/BT.656 Digital YCbCr 4:2:2

–

135-, 216-, and 270-MHz ARM926EJ-S Clock

(8-/16-Bit) Interface

Rate

• Supports digital HDTV (720p/1080i)

–

Fully Software-Compatible With ARM9™

output for connection to external

–

Extended temperature support for 135- and

encoder

216-MHz devices

• External Memory Interfaces (EMIFs)

• ARM926EJ-S Core

–

DDR2 and mDDR SDRAM 16-bit wide EMIF

–

Support for 32-Bit and 16-Bit (Thumb Mode)

With 256 MByte Address Space (1.8-V I/O)

Instruction Sets

–

Asynchronous16-/8-bit Wide EMIF (AEMIF)

–

DSP Instruction Extensions and Single

• Flash Memory Interfaces

Cycle MAC

–

NAND (8-/16-bit Wide Data)

–

ARM® Jazelle® Technology

–

OneNAND(16-bit Wide Data)

–

EmbeddedICE-RT™ Logic for Real-Time

Debug

• Flash Card Interfaces

–

Two Multimedia Card (MMC) / Secure

• ARM9 Memory Architecture

Digital (SD/SDIO)

–

16K-Byte Instruction Cache

–

SmartMedia

–

8K-Byte Data Cache

• Enhanced Direct-Memory-Access (EDMA)

–

32K-Byte RAM

Controller (64 Independent Channels)

–

8K-Byte ROM

• USB Port with Integrated 2.0 High-Speed PHY

–

Little Endian

that Supports

• MPEG4/JPEG Coprocessor

–

USB 2.0 Full and High-Speed Device

–

Fixed Function Coprocessor Supports:

–

USB 2.0 Low, Full, and High-Speed Host

• MPEG4 SP Codec at HD (720p), D1,

• Three 64-Bit General-Purpose Timers (each

VGA, SIF

configurable as two 32-bit timers)

• JPEG Codec up to 50M Pixels per

• One 64-Bit Watch Dog Timer

Second

• Three UARTs (One fast UART with RTS and

• Video Processing Subsystem

CTS Flow Control)

–

Front End Provides:

• Three Serial Port Interfaces (SPI) each with

• Hardware IPIPE for Real-Time Image

two Chip-Selects

Processing

• One Master/Slave Inter-Integrated Circuit (I2C)

• Up to 14-bit CCD/CMOS Digital Interface

Bus®

• 16-/8-bit Generic YcBcR-4:2 Interface

• Two Audio Serial Port (ASP)

(BT.601)

–

I2S and TDM I2S

• 10-/8-bit CCIR6565/BT655 Interface

–

AC97 Audio Codec Interface

• Up to 75-MHz Pixel Clock

–

S/PDIF via Software

• Histogram Module

–

Standard Voice Codec Interface (AIC12)

• Resize Engine

–

SPI Protocol (Master Mode Only)

–

Resize Images From 1/16x to 8x

• Four Pulse Width Modulator (PWM) Outputs

–

Separate Horizontal/Vertical Control

• Four RTO (Real Time Out) Outputs

–

Two Simultaneous Output Paths

• Up to 104 General-Purpose I/O (GPIO) Pins

–

Back End Provides:

(Multiplexed with Other Device Functions)

• Hardware On-Screen Display (OSD)

• On-Chip ARM ROM Bootloader (RBL) to Boot

• Composite NTSC/PAL video encoder

From NAND Flash, MMC/SD, or UART

output

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a trademark of Microsoft.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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