1.

General description

The 74LVC169 is a synchronous presettable 4-bit binary counter which features an

internal look-ahead carry circuitry for cascading in high-speed counting applications.

Synchronous operation is provided by having all flip-flops clocked simultaneously so that

the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by

the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation

eliminates the output counting spikes that are normally associated with asynchronous

(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the

LOW-to-HIGH transition of the clock.

The counter is fully programmable; that is, the outputs may be preset to any number

between 0 and its maximum count. Presetting is synchronous with the clock and takes

place regardless of the levels of the count enable inputs. A LOW level on the parallel

enable (pin PE) input disables the counter and causes the data at the Dn input to be

loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of

the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the

counter counts up, when LOW, it counts down.

The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous

applications without additional gating. Instrumental in accomplishing this function are two

count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both

count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed

forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a

LOW-level output pulse with a duration approximately equal to a HIGH level portion of

pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded

stages.

The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing

the control of data input signals in either state of the clock. The only requirement is that

the various inputs attain the desired state at least a set-up time before the next

LOW-to-HIGH transition of the clock and remain valid for the recommended hold time

thereafter.

The parallel load operation takes precedence over the other operations, as indicated in

the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters

the flip-flops on the next LOW-to-HIGH transition of the clock.

74LVC169

Presettable synchronous 4-bit up/down binary counter

Rev. 05 — 8 June 2009

Product data sheet