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74LVC16374ADGG Folha de dados(PDF) 10 Page - NXP Semiconductors |
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74LVC16374ADGG Folha de dados(HTML) 10 Page - NXP Semiconductors |
10 / 19 page 74LVC_LVCH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 23 March 2010 10 of 19 NXP Semiconductors 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 11. Waveforms Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 7. Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency 001aaa256 nCP input nQn output tPHL tPLH tW VOH VI GND VOL VM VM VM 1/fmax Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable performance. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 8. Data set-up and hold times for the nDn input to the nCP input 001aaa257 GND GND th tsu th tsu VM VM VM VI VOH VOL VI nQn output nCP input nDn input |
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