4

DS686PP1

CS4270

8.2 Power Control - Address 02h ........................................................................................................ 35

8.2.1 Freeze (Bit 7) ......................................................................................................................... 35

8.2.2 PDN_ADC (Bit 5) ................................................................................................................... 35

8.2.3 PDN_DAC (Bit 1) ................................................................................................................... 35

8.2.4 Power Down (Bit 0) ............................................................................................................... 35

8.3 Mode Control - Address 03h ......................................................................................................... 36

8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) ...................................................... 36

8.3.2 Ratio Select (Bits 3:1) ............................................................................................................ 36

8.3.3 PopguardTM Disable (Bit 0) .................................................................................................. 36

8.4 ADC and DAC Control - Address 04h ........................................................................................... 36

8.4.1 ADC HPF Freeze A (Bit 7) .................................................................................................... 36

8.4.2 ADC HPF Freeze B (Bit 6) .................................................................................................... 37

8.4.3 Digital Loopback (Bit 5) ......................................................................................................... 37

8.4.4 DAC Digital Interface Format (Bits 4:3) ................................................................................. 37

8.4.5 ADC Digital Interface Format (Bit 0) ...................................................................................... 37

8.5 Transition Control - Address 05h ................................................................................................... 38

8.5.1 DAC Single Volume (Bit 7) .................................................................................................... 38

8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................................... 38

8.5.3 Invert Signal Polarity (Bits 4:1) .............................................................................................. 38

8.5.4 De-Emphasis Control (Bit 0) .................................................................................................. 39

8.6 Mute Control - Address 06h .......................................................................................................... 39

8.6.1 Auto-Mute (Bit 5) ................................................................................................................... 39

8.6.2 ADC Channel A & B Mute (Bits 4:3) ...................................................................................... 39

8.6.3 Mute Polarity (Bit 2) ............................................................................................................... 39

8.6.4 DAC Channel A & B Mute (Bits 1:0) ...................................................................................... 39

8.7 DAC Channel A Volume Control - Address 07h ............................................................................ 40

8.8 DAC Channel B Volume Control - Address 08h ............................................................................ 40

9. FILTER PLOTS

................................................................................................................................ 41

10. PARAMETER DEFINITIONS .............................................................................................................. 45

11. PACKAGE DIMENSIONS .................................................................................................................. 46

12. ORDERING INFORMATION .............................................................................................................. 47

13. REVISION HISTORY .......................................................................................................................... 47

LIST OF FIGURES

Figure 1. CS4270 Typical Connection Diagram .......................................................................................... 8

Figure 2. Output Test Load ....................................................................................................................... 11

Figure 3. Maximum Loading ...................................................................................................................... 11

Figure 4. Master Mode, Left-Justified SAI ................................................................................................. 18

Figure 5. Slave Mode, Left-Justified SAI ................................................................................................... 18

Figure 6. Master Mode, I²S SAI ................................................................................................................. 18

Figure 7. Slave Mode, I²S SAI ................................................................................................................... 18

Figure 8. Master and Slave Mode SDIN vrs. SCLK .................................................................................. 18

Figure 9. Format 0, Left-Justified up to 24-Bit Data .................................................................................. 19

Figure 10. Format 1, I²S up to 24-Bit Data ................................................................................................ 19

Figure 11. Format 2, Right-Justified 16-Bit Data. (Available in Control Port Mode only)

Format 3, Right-Justified 24-Bit Data. (Available in Control Port Mode only) ........................................... 19

Figure 12. I²C Mode Control Port Timing .................................................................................................. 20

Figure 13. SPI Control Port Timing ........................................................................................................... 21

Figure 14. De-Emphasis Curve ................................................................................................................. 27

Figure 15. CS4270 Recommended Analog Input Network ....................................................................... 28

Figure 16. A/D THD+N Performance vrs. Input Source Resistance ......................................................... 28

Figure 17. A/D Dynamic Range vrs. Input Source Resistance ................................................................. 29

Figure 18. CS4270 Example Analog Input Network .................................................................................. 30