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ADXRS450BEYZ-RL Folha de dados(PDF) 6 Page - Analog Devices |
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ADXRS450BEYZ-RL Folha de dados(HTML) 6 Page - Analog Devices |
6 / 28 page ADXRS450 Preliminary Technical Data Rev. PrA | Page 6 of 28 12 3 4 5 6 7 14 13 12 11 10 9 8 TOP VIEW (Not to Scale) Figure 4. LCC_V Pin Configuration 1 2 3 4 5 6 7 BACK VIEW (Not to Scale) NC = NO CONNECT 14 13 12 11 10 9 8 Figure 5. LCC_V Pin Configuration, Horizontal Layout Table 5. 14_Lead LCC_V Pin Function Descriptions Pin No. Mnemonic Description 1 AVSS Analog Ground. 2 AVDD Analog Regulated Voltage. See Figure 22 for the applications circuit diagram. 3 MISO Master In/Slave Out. 4 DVDD Digital Regulated Voltage. See Figure 22 for the applications circuit diagram. 5 SCLK SPI Clock. 6 CP5 High Voltage Supply. See Figure 22 for the applications circuit diagram. 7 RSVD Reserved. This pin must be connected to DVSS. 8 RSVD Reserved. This pin must be connected to DVSS. 9 VX High Voltage Switching Node. See Figure 22 for the applications circuit diagram. 10 CS Chip Select. 11 DVSS Digital Signal Ground. 12 MOSI Master Out/Slave In. 13 PSS Switching Regulator Ground. 14 PDD Supply Voltage. |
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