AMIS30600LINI1RG datasheet(6/11 Pages) ONSEMI

Nome de Peças	AMIS30600LINI1RG

Descrição Electrónicos	LIN Transceiver

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Fabricante Electrônico	ONSEMI [ON Semiconductor]

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AMIS−30600

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Table 5. AC ELECTRICAL CHARACTERISTICS ACCORDING TO LIN V13 VCC = 4.75 V to 5.25 V; VBB = 7.3 V to 18 V,VEN

< VENon, TA = −40°C to +125°C; RL = 500 W unless otherwise specified. Load for slope definitions (typical loads) = [L1] 1 nF 1 kW / [L2]

6.8 nF 600 W / [L3] 10 nF 500 W.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_slope_F

Slope Time Falling Edge; (Note 5)

See Figure 5

4

−

24

ms

t_slope_R

Slope Time Rising Edge; (Note 5)

See Figure 5

4

−

24

ms

t_slope_Sym

Slope Time Symmetry; (Note 5)

t_slope_F − t_slope_R

−8

−

+8

ms

T_rec_F

Propagation Delay Bus Dominant to

RxD = Low; (Note 6)

See Figures 4 and 5

2

6

ms

T_rec_R

Propagation Delay Bus Recessive to

RxD = High; (Note 6)

See Figures 4 and 5

6

ms

tWAKE

Wake−up Delay Time

30

100

200

ms

5. Guaranteed by design; not measured for all supply/load combinations on ATE.

6. Not measured on ATE.

Table 6. AC ELECTRICAL CHARACTERISTICS ACCORDING TO LIN v2.0 VCC = 4.75 V to 5.25 V; VBB = 7.3 V to

18 V,VEN < VENon, TA = −40°C to +125°C; RL = 500 W unless otherwise specified. Load for slope definitions (typical loads) = [L1] 1 nF

1 kW / [L2] 6.8 nF 600 W / [L3] 10 nF 500 W.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DYNAMIC RECEIVER CHARACTERISTICS ACCORDING TO LIN v2.0

trx_pdr

Propagation Delay Bus Dominant to

RxD = Low; (Note 7)

See Figure 6

6

ms

trx_pdf

Propagation Delay Bus Recessive to

RxD = High; (Note 7)

See Figure 6

6

ms

trx_sym

Symmetry of Receiver Propagation Delay

trx_pdr − trx_pdf

−2

−

+2

ms

DYNAMIC TRANSMITTER CHARACTERISTICS ACCORDING TO LIN v2.0

D1

Duty Cycle 1 = tBus_rec(min)/(2 x tBit);

See Figure

0.396

0.5

D1

Duty Cycle 1 = tBus_rec(min)/(2 x tBit);

See Figure 6

THRec(max) = 0.744 x Vbat;

THDom(max) = 0.581 x Vbat;Vbat

= 7.0 V to 18 V; tBit = 50 ms

THRec(max) = 0.744 x Vbat;

THDom(max) = 0.581 x Vbat;Vbat

= 7.0V; tBit = 50 ms;

tamb = −40°C

0.366

0.5

D2

Duty Cycle 2 = tBus_rec(max)/(2 x tBit);

See Figure 6

THRec(min) = 0.284 x Vbat;

THDom(min) = 0.422 x Vbat;Vbat

= 7.6 V to 18 V; tBit = 50 ms;

0.5

0.581

7. Not measured on ATE.

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