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TDA19978BHV Folha de dados(PDF) 11 Page - NXP Semiconductors |
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11 / 38 page TDA19978B_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 10 May 2010 11 of 38 NXP Semiconductors TDA19978B Quad HDMI 1.3a receiver with digital processing The TDA19978B includes a two-channel status decoder supporting multi-channel reception for audio sample packets. This enables the user to obtain channel status information from the IEC 60958/IEC 61937 stream such as: • The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958) • Copyright protection • Sampling frequency Refer to IEC 60958/IEC 61937 specifications for more details. An update of each InfoFrame or the channel status content is indicated by a register bit and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary. 8.10 Audio PLL The TDA19978B generates a 128/256/512 × f s system clock enabling the use of simple audio DACs without an integrated PLL, such as the UDA1334BTS. The programming of the audio PLL can be either automatic, using the audio clock regeneration parameters found in the Data Islands or set manually using the I2C-bus. All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz, 96 kHz and 192 kHz are accepted by the device. 8.11 Audio formatter Audio samples can be output in either S/PDIF, I2S-bus formats or DSD (SACD). In I2S-bus or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins (AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using these pins. The audio port mapping depends on the channel allocation (see Table 4, Table 5 and Table 6 for detailed information). |
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