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DAC5682Z Folha de dados(PDF) 10 Page - Texas Instruments |
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DAC5682Z Folha de dados(HTML) 10 Page - Texas Instruments |
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10 / 59 page  DAC5682Z SLLS853C – AUGUST 2007 – REVISED JUNE 2009 ........................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Positive 1000 DCLKP/N = 150 MHz Negative –1800 Positive 800 DCLKP/N = 200 MHz Negative –1300 Positive 600 DCLKP/N = 250 MHz Negative –1000 Positive 450 DLL Enabled, DCLKP/N = 300 MHz Negative –800 tSKEW(A), CONFIG5 DCLK to Data Skew(2) ps tSKEW(B) DLL_bypass = 0, Positive 400 DCLKP/N = 350 MHz DDR format Negative –700 Positive 300 DCLKP/N = 400 MHz Negative –600 Positive 300 DCLKP/N = 450 MHz Negative –500 Positive 350 DCLKP/N = 500 MHz Negative –300 DLL Disabled, CONFIG5 DLL_bypass = 1, DDR format, 250 DCLKP frequency: <125 MHz Input fDATA MSPS data rate supported DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format, 250 1000 DCLKP frequency: 125 to 500 MHz CONFIG10 = '11001101' = 0xCD 125 150 DLL Enabled, CONFIG10 = '11001110' = 0xCE 150 175 DLL Operating Frequency CONFIG5 CONFIG10 = '11001111' = 0xCF 175 200 MHz (DCLKP/N Frequency) DLL_bypass = 0, CONFIG10 = '11001000' = 0xC8 200 325 DDR format CONFIG10 = '11000000' = 0xC0 325 500 CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB VIH High-level input voltage 2 3 V VIL Low-level input voltage 0 0 0.8 V IIH High-level input current ±20 µA IIL Low-level input current ±20 µA CI CMOS Input capacitance 5 pF IOVDD Iload = –100 µA V –0.2 VOH SDO, SDIO 0.8 Iload = –2mA V x IOVDD Iload = 100 µA 0.2 V VOL SDO, SDIO Iload = 2 mA 0.5 V Setup time, SDENB to ts(SDENB) 20 ns rising edge of SCLK Setup time, SDIO valid to ts(SDIO) 10 ns rising edge of SCLK Hold time, SDIO valid to th(SDIO) 5 ns rising edge of SCLK t(SCLK) Period of SCLK 100 ns t(SCLKH) High time of SCLK 40 ns t(SCLKL) Low time of SCLK 40 ns (2) Positive skew: Clock ahead of data. Negative skew: Data ahead of clock. 10 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5682Z |
Nº de peça semelhante - DAC5682Z_09 |
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Descrição semelhante - DAC5682Z_09 |
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