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CDCEL937PW Folha de dados(PDF) 3 Page - Texas Instruments |
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CDCEL937PW Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 30 page EEPROM Xin/CLK Xout VDD GND InputClock Vctr Vddout VCXO XO LVCMOS Y1 Y2 LV CMOS Pdiv1 10-Bit Y3 Y4 Y5 Y6 LV CMOS Pdiv7 Pdiv6 LV CMOS LV CMOS Pdiv5 Pdiv4 LV CMOS LV CMOS Pdiv3 Pdiv2 7-Bit LV CMOS Programming and SDA/SCL Register Y7 PLL Bypass PLL1 withSSC PLL Bypass PLL 2 withSSC PLL Bypass PLL 3 withSSC S0 S1/SDA S2/SCL 7-Bit 7-Bit 7-Bit 7-Bit 7-Bit CDCE937 CDCEL937 www.ti.com SLAS564F – AUGUST 2007 – REVISED MARCH 2010 FUNCTIONAL BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VDD Supply voltage range –0.5 to 2.5 V VI Input voltage range(2) (3) –0.5 to VDD + 0.5 V VO Output voltage range(2) –0.5 to Vddout + 0.5 V II Input current (VI < 0, VI > VDD) 20 mA IO Continuous output current 50 mA Tstg Storage temperature range –65 to 150 °C TJ Maximum junction temperature 125 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table. Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): CDCE937 CDCEL937 |
Nº de peça semelhante - CDCEL937PW |
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Descrição semelhante - CDCEL937PW |
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