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AD5433YRU Folha de dados(PDF) 3 Page - Analog Devices

Nome de Peças AD5433YRU
Descrição Electrónicos  8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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AD5424/AD5433/AD5445
Rev. B | Page 3 of 32
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance measured with OP177and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5424
Resolution
8
Bits
Relative Accuracy
±0.25
LSB
Differential Nonlinearity
±0.5
LSB
Guaranteed monotonic
AD5433
Resolution
10
Bits
Relative Accuracy
±0.5
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
AD5445
Resolution
12
Bits
Relative Accuracy
±1
LSB
Differential Nonlinearity
–1/+2
LSB
Guaranteed monotonic
Gain Error
±10
mV
Gain Error Temperature Coefficient1
±5
ppm FSR/°C
Output Leakage Current1
±10
nA
Data = 0×0000, TA = 25°C, IOUT1
±20
nA
Data = 0×0000, T = −40°C to +125°C, IOUT1
REFERENCE INPUT1
Reference Input Range
±10
V
VREF Input Resistance
8
10
12
Input resistance TC = –50 ppm/°C
RFB Resistance
8
10
12
Input resistance TC = –50 ppm/°C
Input Capacitance
Code Zero Scale
3
6
pF
Code Full Scale
5
8
pF
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH
1.7
V
Input Low Voltage, VIL
0.6
V
Output High Voltage, VOH
VDD − 1
V
VDD = 4.5 V to 5 V, ISOURCE = 200 μA
VDD − 0.5
V
VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA
Output Low Voltage, VOL
0.4
V
VDD = 4.5 V to 5 V, ISINK = 200 μA
0.4
V
VDD = 2.5 V to 3.6 V, ISINK = 200 μA
Input Leakage Current, IIL
1
μA
Input Capacitance
4
10
pF
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
10
MHz
VREF = ±3.5 V; DAC loaded all 1s
Output Voltage Settling Time
VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch
alternately loaded with 0s and 1s
Measured to ±16 mV of full scale
30
60
ns
Measured to ±4 mV of full scale
35
70
ns
Measured to ±1 mV of full scale
80
120
ns
Digital Delay
20
40
ns
Interface delay time
10% to 90% Settling Time
15
30
ns
Rise and fall time, VREF = 10 V, RLOAD = 100 Ω
Digital-to-Analog Glitch Impulse
2
nV-s
1 LSB change around major carry, VREF = 0 V
Multiplying Feedthrough Error
DAC latch loaded with all 0s, VREF = ±3.5 V
70
dB
Reference = 1 MHz
48
dB
Reference = 10 MHz


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