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KM416V4004C Folha de dados(PDF) 9 Page - Samsung semiconductor |
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KM416V4004C Folha de dados(HTML) 9 Page - Samsung semiconductor |
9 / 36 page KM416V4004C,KM416V4104C CMOS DRAM tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to earlier CAS falling before RAS transition low. tCHR is referenced to the later CAS rising high after RAS transition low. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. tASC ≥6ns, Assume tT=2.0ns, if tASC≤6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC". If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. tCSR tCHR RAS LCAS UCAS tDS tDH LCAS UCAS DQ0 ~ DQ15 Din 22. 21. 20. 19. 18. 17. 16. 23. 24. |
Nº de peça semelhante - KM416V4004C |
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Descrição semelhante - KM416V4004C |
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