KM681002C/CL, KM681002CI/CLI

CMOS SRAM

PRELIMINARY

Revision 2.0

- 4 -

March 2000

PRELIMINARY

TEST CONDITIONS*

Parameter

Value

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

3ns

Input and Output timing Reference Levels

1.5V

Output Loads

See below

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

KM681002C-10

KM681002C-12

KM681002C-15

KM681002C-20

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Read Cycle Time

10

-

12

-

15

-

20

-

ns

Address Access Time

-

10

-

12

-

15

-

20

ns

Chip Select to Output

-

10

-

12

-

15

-

20

ns

Output Enable to Valid Output

-

5

-

6

-

7

-

9

ns

Chip Enable to Low-Z Output

3

-

3

-

3

-

3

-

ns

Output Enable to Low-Z Output

0

-

0

-

0

-

0

-

ns

Chip Disable to High-Z Output

0

5

0

6

0

7

0

9

ns

Output Disable to High-Z Output

0

5

0

6

0

7

0

9

ns

Output Hold from Address

3

-

3

-

3

-

3

-

ns

Chip Selection to Power Up Time

0

-

0

-

0

-

0

-

ns

Chip Selection to Power Down-

-

10

-

12

-

15

-

20

ns

Output Loads(B)

5pF*

480

Ω

255

Ω

+5.0V

* Including Scope and Jig Capacitance

Output Loads(A)

Ω

Ω

30pF*

* Capacitive Load consists of all components of the

test environment.