Rev 1.0

KM718FV4021

128Kx36 & 256Kx18 SRAM

- 4 -

KM736FV4021

Dec. 1998

FUNCTION DESCRIPTION

The KM736FV4021 and KM718FV4021 are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072words of 36

bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNG

′s advanced CMOS technology.

Single differential PECL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the

rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are

updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one

cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second-

edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this

cycle, signaling that the SRAM should drive out the data.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write(Store) Operation

All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,

one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the

Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.

Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write

cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of

read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the

same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to

be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address

is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the

SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have

new byte data from the write data buffer and the other bytes from the SRAM array.

Low Power Dissipation Mode

During normal operation, asynchronous signal ZZ must be pulled low. Low Power Mode is enabled by switching ZZ high. When the

SRAM is in Power Down Mode, the outputs will go to a Hi-Z state and the SRAM will draw standby current. SRAM data will be pre-

TRUTH TABLE

K

ZZ

G

SS

SW

SWa

SWb

SWc

SWd

DQa

DQb

DQc

DQd

Operation

X

H

X

X

X

X

X

X

X

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Power Down Mode. No Operation

X

L

H

X

X

X

X

X

X

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Output Disabled.

↑

L

L

H

X

X

X

X

X

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Output Disabled. No Operation

↑

L

L

L

H

X

X

X

X

↑

L

X

L

L

H

H

H

H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

No Bytes Written

↑

L

X

L

L

L

H

H

H

Hi-Z

Hi-Z

Hi-Z

Write first byte

↑

L

X

L

L

H

L

H

H

Hi-Z

Hi-Z

Hi-Z

Write second byte

↑

L

X

L

L

H

H

L

H

Hi-Z

Hi-Z

Hi-Z

Write third byte

↑

L

X

L

L

H

H

H

L

Hi-Z

Hi-Z

Hi-Z

Write fourth byte

↑

L

X

L

L

L

L

L

L

Write all byte