8

FN7627.0

July 2, 2010

FIGURE 4. CAPACITANCE TEST CIRCUIT

FIGURE 5. CROSSTALK TEST CIRCUIT

FIGURE 6A. MEASUREMENT POINTS

FIGURE 6B. TEST CIRCUIT

FIGURE 6. SKEW TEST

VDD

C

GND

HSDxx

Dx

SEL

IMPEDANCE

ANALYZER

0V OR

Repeat test for all switches.

OE

VDD

ANALYZER

VDD

C

HSD1x

SIGNAL

GENERATOR

GND

SEL

Dx

50

Ω

NC

Dx

HSD2x

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

OE

VIN

DIN+

DIN-

OUT+

OUT-

50%

50%

90%

10%

10%

10%

10%

90%

90%

50%

90%

50%

OUT+

COMD1

D2

GND

VDD

C

D1

COMD2

OUT-

DIN+

DIN-

|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.

|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.

|tskew_0| Change in Skew through the Switch for Output Signals.

|tskew_i| Change in Skew through the Switch for Input Signals.

15.8

Ω

15.8

Ω

143

Ω

143

Ω

45

Ω

45

Ω

SEL

VIN

OE

ISL54225