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ISL54100ACQZ Folha de dados(PDF) 10 Page - Intersil Corporation |
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ISL54100ACQZ Folha de dados(HTML) 10 Page - Intersil Corporation |
10 / 21 page 10 FN6725.0 June 17, 2008 0x03 Input Control (0x12) Recommended default: 0x62 0 Tri-state Unselected Clock Inputs 0: Normal Operation 1: Termination of unselected TMDS clock inputs is tri-stated to save power. Setting this bit will disable the activity detect function. This bit should not be set in crosspoint configuration because it will make the clock termination resistance variable depending on which 2 inputs are selected. In general, this bit should always be set to 0. 1 Tri-state Unselected Data Inputs 0: Normal Operation 1: Unselected Data inputs are tri-stated to save power. This bit should not be set in crosspoint configuration because it will make the data input termination resistance variable depending on which 2 inputs are selected. (default) 2 Tri-state Selected Clock Inputs 0: Selected Clock inputs are terminated into 50 Ω/100Ω. 1: Selected Clock inputs are tri-stated (to allow chip to operate in parallel with another TMDS receiver with fixed 50 Ω termination) 3 Tri-state Selected Data Inputs 0: Selected Data inputs are terminated into 50 Ω/100Ω. 1: Selected Data inputs are tri-stated (to allow chip to operate in parallel with another TMDS receiver with fixed 50 Ω termination) 4 Activity Detect Mode 0: AC Activity. Activity detection is based on the presence of AC activity on TMDS clock inputs. This setting (along with a hysteresis of 20mV enabled) provides reliable activity detection. (recommended setting) 1: Common Mode Voltage. If the common mode voltage is above ~3.05V, the input is considered inactive. This method has been found to be unreliable with small signal swings and should not be used. This setting is the silicon default but should be changed in software for more reliable activity detection. 5 Clock Rx Hysteresis Enables hysteresis for the clock inputs to prevent false clock detection when both inputs are high. Data inputs do not get hysteresis. 0: TMDS input hysteresis disabled 1: TMDS input hysteresis enabled. Eliminates false activity detects on unconnected channels. (recommended setting) 6 Clock Rx Hysteresis Magnitude Controls the amount of hysteresis in the clock inputs. 0: 10mV 1: 20mV (recommended setting) 7 Recalibrate 0: Normal Operation 1: Recalibrates termination resistance. To recalibrate, take this bit high, wait at least 1ms, then take this bit low. Calibration is automatically done after power-on, but performing a recalibration after the supply voltage and temperature have stabilized may result in termination resistances closer to the desired 50 Ω. Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION ISL54100A, ISL54101A, ISL54102A |
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