4

FN6456.0

September 28, 2007

Pin Descriptions (Pin Numbers and Names are Related)

PIN NUMBER

PIN NAME

PIN FUNCTION

5, 32

12VINA, 12VINB

Provides 12VMAIN power supply and the high side of the sense resistor inputs. This must be a Kelvin

connection between IC and sense resistor. An undervoltage lockout circuit (UVLO) prevents the switches

from turning on while this input is less than its lockout threshold.

12, 25

3VINA, 3VINB

Provides 3.3VMAIN power supply and the high side of the sense resistor inputs. This must be a Kelvin

connection between IC and sense resistor. An undervoltage lockout circuit (UVLO) prevents the switches

from turning on while this input is less than its lockout threshold.

16, 21

3VOUTA, 3VOUTB 3.3VOUT. Connected to 3.3V FET source. These are used to monitor the 3.3V output voltages for Power

Good status.

10, 27

12VOUTA,

12VOUTB

12VOUT. Connected to 12V FET drain. These are used to monitor the 3.3V output voltages for Power

Good status.

8, 29

12VSENSEA,

12VSENSEB

12VMAIN low side of sense resistor connection. When either current limit threshold of the load current

across the sense resistor = 50mV is reached, the related 12VGATE pin is modulated to maintain a

constant voltage across the sense resistor and thus a constant current into the load. If the 50mV threshold

is exceeded for tFLT, the isolation protection is tripped and the GATE pin for the affected supply’s external

MOSFET is immediately pulled high. This must be a Kelvin connection between IC and sense resistor.

13, 24

3VSENSEA,

3VSENSEB

3.3VMAIN low side of sense resistor connection. When either current limit threshold of the load current

across the sense resistor = 50mV is reached, the related 3V GATE pin is modulated to maintain a constant

voltage across the sense resistor and thus a constant current into the load. If the 50mV threshold is

exceeded for tFLT, the isolation protection is tripped and the GATE pin for the affected supply’s external

MOSFET is immediately pulled low. This must be a Kelvin connection between IC and sense resistor.

3, 34

12VGATEA

12VGATEB

12V Gate Drive Outputs: Each pin connects to the gate of an external P-Channel MOSFET. During

power-up, the CGATE and the CGS of the MOSFETs are connected to a 25µA current sink. This controls

the value of dv/dt seen at the source of the MOSFETs. During current limit events, the voltage at this pin

is adjusted to maintain constant current through the switch for a period of tFLT. Whenever an overcurrent,

thermal shutdown, or input undervoltage fault condition occurs, the GATE pin for the affected slot is

immediately brought high. These pins are charged by an internal current source during power-down.

14, 23

3VGATEA

3VGATEB

3V Gate Drive Outputs: Each pin connects to the gate of an external N-Channel MOSFET. During power-

up, the CGATE and the CGS of the MOSFETs are connected to a 25µA current source. This controls the

value of dv/dt seen at the source of the MOSFETs, and hence the current flowing into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain constant current through the

switch for a period of tFLT. Whenever an overcurrent, thermal shutdown, or input undervoltage fault

condition occurs, the GATE pin for the affected slot is immediately brought low. During power-down, these

pins are discharged by an internal current source.

11, 26

VSTBYA, VSTBYB

3.3V Standby Input Voltage: Required to support PCI Express VAUX output. Additionally, the SMBus logic

and internal registers run off of VSTBY to ensure that the chip is accessible during standby modes. A

UVLO circuit prevents turn-on of this supply until VSTBY rises above its UVLO threshold. Both pins must

be externally connected together at the ISL6112 controller.

15, 22

VAUXA, VAUXB

3.3VAUX Outputs to PCI Express Card Slots: These outputs connect the 3.3AUX pin of the PCI Express

connectors to VSTBY via internal 400m

Ω MOSFETs. These outputs are 1A current limited and protected

against short-circuit faults.

44, 43

ONA, ONB

Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA and MAINB (+3.3V and +12V)

outputs. Taking ON low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie

these pins to GND if using SMI power control. Also, see pin description for FAULTA and FAULTB.

45, 42

AUXENA, AUXENB Level sensitive auxiliary enable Inputs. Used to enable or disable the VAUX outputs. Taking AUXEN low

after a fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power

control. Also, see pin description for FAULTA and FAULTB.

2, 35

CFILTERA,

CFILTERB

invoked.

6, 31

PWRGDA

PWRGDB

Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has been commanded to turn on

and has successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin

ISL6112