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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ISL12024IBZ Folha de dados(PDF) 4 Page - Intersil Corporation |
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ISL12024IBZ Folha de dados(HTML) 4 Page - Intersil Corporation |
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4 / 25 page  4 FN6370.1 October 18, 2006 EEPROM Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS EEPROM Endurance 2,000,000 Cycles EEPROM Retention Temperature ≤ +75°C 50 Years Serial Interface (I2C) Specifications DC Electrical Specifications SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIL SDA, and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA, and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x VDD V VOL SDA Output Buffer LOW Voltage IOL = 4mA 0 0.4 V ILI Input Leakage Current on SCL VIN = 5.5V 100 nA ILO I/O Leakage Current on SDA VIN = 5.5V 100 nA AC Electrical Specifications SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS fSCL SCL Frequency 400 kHz tIN Pulse width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VDD to SDA entering the 30% to 70% of VDD window. 0ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. 600 ns ISL12024 |
Nº de peça semelhante - ISL12024IBZ |
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Descrição semelhante - ISL12024IBZ |
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