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LM26001BMHX Folha de dados(PDF) 10 Page - National Semiconductor (TI) |
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LM26001BMHX Folha de dados(HTML) 10 Page - National Semiconductor (TI) |
10 / 18 page ramps down to zero again. Until the next cycle, the inductor current remains at zero. At nominal load currents, in FPWM mode, the device operates in continuous conduction mode, where positive current always flows in the inductor. Typical discontinuous operation waveforms are shown below. 30001923 FIGURE 4. Discontinuous Mode Waveforms 75mA Load, Vin = 12V At very light load, in FPWM mode, the LM26001B may enter sleep mode. This is to prevent an over-voltage condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation. ENABLE The LM26001B provides a shutdown function via the EN pin to disable the device when the output voltage does not need to be maintained. EN is an analog level input with typically 120 mV of hysteresis. The device is active when the EN pin is above 1.2V (typical) and in shutdown mode when EN is below this threshold. When EN goes high, the internal VDD regulator turns on and charges the VDD capacitor. When VDD reaches 3.9V (typical), the soft-start pin begins to source current. In shutdown mode, the VDD regulator shuts down and total quiescent current is reduced to 10 µA (typical). Be- cause the EN pin sources 4.5 µA (typical) of pull-up current, this pin can be left open or connected to VIN for always-on operation. When open, EN will be pulled up to VIN. SOFT-START The soft-start feature provides a controlled output voltage ramp up at startup. This reduces inrush current and eliminates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At power-on, enable, or UVLO recovery, an internal 2.2 µA (typical) current charges the soft-start capacitor. During soft-start, the error amplifier output voltage is controlled by both the soft-start voltage and the feedback loop. As the SS pin voltage ramps up, the duty cycle increases proportional to the soft-start ramp, causing the output voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft-start ca- pacitor. The higher the capacitance, the slower the output voltage ramps up. The soft-start capacitor value can be cal- culated with the following equation: Where tss is the desired soft-start time and Iss is the soft-start source current. During soft-start, current limit and synchro- nization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends when the SS pin voltage reaches 1.23V typical. At this point, output voltage control is transferred to the FB pin and the SS pin is dis- charged. CURRENT LIMIT The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To ensure accurate current sensing, VIN should be bypassed with a minimum 1µF ceramic capacitor placed directly at the pin. When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing inductor cur- rent to ramp down until the next cycle. This reduction in duty cycle corresponds to a reduction in output voltage. The current limit comparator is disabled for less than 100ns at the leading edge for increased immunity to switching noise. Because the current limit monitors peak inductor current, the DC load current limit threshold varies with inductance and frequency. Assuming a minimum current limit of 1.80A, max- imum load current can be calculated as follows: Where Iripple is the peak-to-peak inductor ripple current, cal- culated as shown below: To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit specifica- tion. During high over-current conditions, such as output short cir- cuit, the LM26001B employs frequency foldback as a second level of protection. If the feedback voltage falls below the short circuit threshold of 0.9V, operating frequency is reduced, thereby reducing average switch current. This is especially helpful in short circuit conditions, when inductor current can rise very high during the minimum on-time. Frequency reduc- tion begins at 20% below the nominal frequency setting. The minimum operating frequency in foldback mode is 71 kHz typical. If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the typical performance charac- teristics section. In conditions where the on time is close to minimum (less than 200nsec typically), such as high input voltage and high switching frequency, the current limit may not function prop- erly. This is because the current limit circuit cannot reduce the on-time below minimum which prevents entry into frequency foldback mode. There are two ways to ensure proper current limit and foldback operation under high input voltage condi- tions. First, the operating frequency can be reduced to in- crease the nominal on time. Second, the inductor value can be increased to slow the current ramp and reduce the peak over-current. www.national.com 10 |
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