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LB1872 Folha de dados(PDF) 9 Page - Sanyo Semicon Device

Nome de Peças LB1872
Descrição Electrónicos  Polygon Mirror Scanner Driver IC
Download  11 Pages
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Fabricante Electrônico  SANYO [Sanyo Semicon Device]
Página de início  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LB1872 Folha de dados(HTML) 9 Page - Sanyo Semicon Device

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No. 5625-9/11
LB1872
Continued from preceding page.
Pin No.
Symbol
Pin function
Equivalent circuit
26
FGIN
FG amplifier input
27
AGC
AGC amplifier frequency characteristics correction
Insert a capacitor (about 0.1 µF) between this pin and ground.
28
GND
Ground
LB1872 Functional Description
1. Speed control circuit
Since this IC adopts a PLL speed control circuit, it can provide high-precision, jitter-free, and stable motor operation.
This PLL circuit compares the phases of the CLK (external clock) rising edge and the FG Schmitt output rising edge
and uses the error output from that comparison for control.
If an internal clock system is used, the FG servo frequency is determined by the following formula. Therefore, the
motor speed can be set by setting the number of FG pulses and the crystal oscillator frequency.
fFG(servo) = fOSC/N
fOSC: Crystal oscillator frequency
N: Clock divisor (See the separately provided table.)
If an external clock (input to the N1 pin) is used, the IC controls the motor speed by holding the FG servo frequency
identical to the external clock frequency.
2. Output drive circuit
To suppress motor noise as much as possible, this IC adopts a three-phase full wave current linear drive technique.
Also, it adopts a midpoint control technique to prevent ASO destruction of the output transistors.
This IC uses short-circuit braking (lower side output) for motor deceleration during speed switching and lock pull in.
In stop mode, the output is turned off.
If a motor with a coil resistance (interphase) of 10
Ω or lower is used, diodes (rectifying) may be inserted between the
outputs and ground (for all outputs) and current limitation may also be applied during braking to prevent excessive
braking currents. Although this is disadvantageous from an ASO standpoint, since states with a large back EMF are
states with a high switching frequency and the amount of time during which loads are applied to the transistors will
be shorter, ASO problems will not be particular severe.
3. Current limiter circuit
The current limiter circuit is a peak current limiter whose limit current is determined by I = VRF/Rf (where VRF = 0.5
V (typical) and Rf is the current detection resistor).


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