ISL29028A

8

FN7721.1

February 8, 2011

Principles of Operation

as 0b100010<x>, where “0b” signifies binary notation and x

represents the logic level on pin ADDR0.

always drives the SCL (clock) line, while either the master or the

with the master asserting a start condition (SDA falling while SCL

remains high). The first transmitted byte is initiated by the

master and includes 7 address bits and a R/W bit. The slave is

responsible for pulling SDA low during the ACK bit after every

transmitted byte.

condition (SDA rising while SCL remains high).

Photodiodes and ADCs

The ISL29028A contains two photodiode arrays which convert

photons (light) into current. The ALS photodiodes are constructed to

mimic the human eye’s wavelength response curve to visible light

(see Figure 6). The ALS photodiodes’ current output is digitized by a

12-bit ADC in 100ms. These 12 bits can be accessed by reading

completed.

The ALS converter is a charge-balancing integrating 12-bit ADC.

Charge-balancing is best for converting small current signals in the

presence of periodic AC noise. Integrating over 100ms highly rejects

both 50Hz and 60Hz light flicker by picking the lowest integer

number of cycles for both 50Hz/60Hz frequencies.

TABLE 11. REGISTER 0x09 (ALSIR_DT1) - ALS/IR SENSOR DATA (LOWER 8 BITS)

BIT #

ACCESS

DEFAULT

BIT NAME

FUNCTION/OPERATION

7:0

RO

0x00

ALSIR_DATA

(ALS/IR Data)

Lower 8 bits (of 12 bits) from result of ALS/IR sensor conversion

TABLE 12. REGISTER 0x0A (ALSIR_DT2) - ALS/IR SENSOR DATA (UPPER 4 BITS)

BIT #

ACCESS

DEFAULT

BIT NAME

FUNCTION/OPERATION

7:4

RO

0x00

(Unused)

Unused bits

3:0

RO

0x00

ALSIR_DATA

(ALS/IR Data)

Upper 4 bits (of 12 bits) from result of ALS/IR sensor conversion

TABLE 13. REGISTER 0x0E (TEST1) - TEST MODE

BIT #

ACCESS

DEFAULT

BIT NAME

FUNCTION/OPERATION

7:0

RW

0x00

(Write as 0x00)

Test mode register. When 0x00, in normal operation

TABLE 14. REGISTER 0x0F (TEST2) - TEST MODE 2

BIT #

ACCESS

DEFAULT

BIT NAME

FUNCTION/OPERATION

7:0

RW

0x00

(Write as 0x00)

Test mode register. When 0x00, in normal operation

START

W A

A

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A

A6 A5 A4 A3 A2 A1 A0 W A

A

A

A D7 D6 D5 D4 D3D2 D1D0

13

5

7

13

57

12 3

4 5

6

9

2

4

6

STOP START

SDA DRIVEN BY MASTER

DEVICE ADDRESS

SDA DRIVEN BY ISL29028A

DATA BYTE0

REGISTER ADDRESS

SLAVE

DEVICE ADDRESS

SDA DRIVEN BY MASTER

SDA DRIVEN BY MASTER

24

68 9

2

468 9

7

8

1

357 8

9

MASTER

(ISL29028A)