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LS7766 Folha de dados(PDF) 4 Page - LSI Computer Systems |
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LS7766 Folha de dados(HTML) 4 Page - LSI Computer Systems |
4 / 14 page MCR0 : The MCR0 is an 8-bit read/write register which configures the counting modes and the index input functionality. Upon power-up, the MCR0 is cleared to zero. MCR0: B7 B6 B5 B4 B3 B2 B1 B0 B1B0 = 00: Non-quadrature count mode (A = clock, B = direction). = 01: x1 quadrature count mode (one count per quadrature cycle). = 10: x2 quadrature count mode (two counts per quadrature cycle). = 11: x4 quadrature count mode (four counts per quadrature cycle). B3B2 = 00: Free-running count mode. = 01: Single-cycle count mode (CNTR disabled with carry and borrow, re-enabled with reset or load) = 10: Range-limit count mode (up and down count ranges are limited between IDR and zero, respectively. Counting freezes at these limits but resumes when the direction is reversed) = 11: Modulo-n count mode (input count clock frequency is divided by a factor of [n+1], where n = IDR. In up direction, the CNTR is cleared to 0 at CNTR = IDR and up count continues. In down direction, the CNTR is preset to the value of IDR at CNTR = 0 and down count continues. A mod-n rollover marker pulse is generated at each limit at the FLGa output). B5B4 = 00: Disable INDX/ input. = 01: Configure INDX/ input as the load_CNTR input (transfers IDR to CNTR). = 10: Configure INDX/ as the reset _CNTR input (clears CNTR to 0). = 11: Configure INDX/ as the load_ODR input (transfers CNTR to ODR). B6 = 0: Asynchronous index. = 1: Synchronous index (overridden in non-quadrature mode). B7 = 0: Input filter clock (PCK) division factor = 1. Filter clock frequency = fPCK. = 1: Input filter clock division factor = 2. Filter clock frequency = fPCK/2. MCR1: The MCR1 is an 8-bit read/write register which configures the FLGa and FLGb output functionality. In addition, the MCR1 can be used to enable/disable counting.Upon power-up, the MCR1 is cleared to zero: MCR1: B7 B6 B5 B4 B3 B2 B1 B0 B0 = 1: Enable Carry on FLGa (flags CNTR overflow; latched or unlatched logic low on carry). B1 = 1: Enable Borrow on FLGa (flags CNTR underflow, latched or unlatched logic low on borrow). B2 = 1: Enable Compare on FLGa (In free-running count mode a latched or unlatched logic low is generated in both up and down count directions at CNTR = IDR. In contrast, in range-limit and mod-n count modes a latched or unlatched low is generated at CNTR = IDR in the up-count direction only. B3 = 1: Enable index on FLGa (flags index, latched or unlatched logic low when INDX input is at active level) B5B4 = 00: FLGb disabled (fixed high) = 01: FLGb = Sign, high for negative signifying CNTR underflow, low for positive. = 10: FLGb = Up/Down count direction, high in count-up, low in count-down. B6 = 0: Enable counting. = 1: Disable counting. B7 = 0: FLGa is latched. = 1: FLGa is non-latched and instantaneous. NOTE: Carry, Borrow, Compare and Index can all be simultaneously enabled on FLGa. 7766-111406-4 |
Nº de peça semelhante - LS7766 |
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Descrição semelhante - LS7766 |
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