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LC74792 Folha de dados(PDF) 3 Page - Sanyo Semicon Device |
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LC74792 Folha de dados(HTML) 3 Page - Sanyo Semicon Device |
3 / 25 page No. 5965-3/25 LC74792, 74792JM Pin Functions Pin No. Pin Function Description 1 VSS1 Ground Digital system ground 2 XtalIN Crystal oscillator connections Connections for the crystal element and capacitors that form the crystal oscillator. Also 3 XtalOUT used for external clock input (fsc, 2fsc, or 4fsc). 4 CTRL1 Crystal element switching Switches between external clock input mode and crystal oscillator mode. Set this pin low for crystal oscillator, and high for external clock input. 5 CS Enable input pin Enable input pin (hysteresis input) 6 SIO Data input/output pin Data input/output pin (hysteresis input) 7 SCLK Clock input pin Clock input pin (hysteresis input) External synchronizing signal presence/absence discrimination status output. 8 SYNCJDG External synchronizing signal A high level is output when synchronizing signals are present. discrimination output This pin outputs the crystal oscillator clock when the RST pin is low. (This reset state output can be disabled with command input.) 9 Hout Horizontal synchronizing signal output Horizontal synchronizing signal output 10 VSS2 Ground Ground. (VCO circuit ground) 11 CPOUT Charge pump output Charge pump output. Connect a low-pass filter to this pin. 12 VCOIN Oscillator control voltage input VCO oscillation control voltage input 13 VCOR Oscillator range adjustment VCO oscillation range adjustment resistor connection 14 DAV Data acquisition output Outputs a low level when PDC/VPS data has been discriminated 15 VDD2 Power supply (+5 V) Power supply (+5 V) (VCO system power supply) 16 SYNIN Sync separator circuit input Internal sync separator circuit video signal input 17 SEPC Slice level output Slice level verification 18 SEPOUT Composite synchronizing signal output Internal sync separator circuit composite synchronizing signal output Inputs the vertical synchronizing signal by integrating the SEPOUT pin output signal. 19 SEPIN Vertical synchronizing signal input Applications must connect the SEPOUT pin to this pin through an integration circuit. If unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.) Vertical synchronizing signal output 20 Vout Vertical synchronizing signal output This pin outputs the VCO clock when the RST pin is low. (This reset state output can be disabled with command input.) Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPIN 21 CTRL2 SEPIN input control input. When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.) When high: The VSYNC signal is input. 22 CDLR Clock phase adjustment Connection for the clock phase adjustment resistor 23 RST Reset input System reset input. A pull-up resistor is built in. (This input has hysteresis characteristics.) 24 VDD1 Power supply (+5 V) Power supply. (+5 V: digital system power supply) |
Nº de peça semelhante - LC74792 |
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Descrição semelhante - LC74792 |
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