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LC74793JM Folha de dados(PDF) 9 Page - Sanyo Semicon Device |
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LC74793JM Folha de dados(HTML) 9 Page - Sanyo Semicon Device |
9 / 24 page No. 5966-9/24 LC74793, 74793JM Command 1 (VPS/PDC control command 1) • First byte DA 0 to 7 Register Contents Notes Status Function 7 — 1 First byte identification bit 6 — 1 Command 1 identification code. 5 — 1 VPS/PDC control settings 1. 4 — 1 3 — 0 2 — 0 1 — 0 0 — 1 • Second byte Data acquisition clock selection. The clock can be shifted relative to the data in units of 8 clock cycles. DA 0 to 7 Register Contents Notes Status Function 7 — 0 Second byte identification bit 6 CPA1 0 1 5 CPA2 0 1 4 CPA0 0 1 3 VPM3 0 1 2 VPM2 0 1 Slicer operating mode selection 1 VPM1 0 1 0 VPM0 0 1 CPA2 CPA1 CPA0 Clock 0 0 0 NO1 0 0 1 NO2 0 1 0 NO3 0 1 1 NO4 1 0 0 NO5 1 0 1 NO6 1 1 0 NO7 1 1 1 NO8 M3 M2 M1 MO Operating mode 0 0 0 0 VPS 0 0 0 1 8/30/2 (PDC) 0 0 1 0 PDC and VPS automatic recognition 1 0 0 1 1 8/30/1 (UDT) 0 1 0 0 Header time 1 0 1 0 1 Header time 2 0 1 1 0 Header time 3 0 1 1 1 Header time 4 1 0 0 0 Status display 1 1 0 0 1 Status display 2 1 0 1 0 Status display 3 1 0 1 1 Status display 4 1 1 0 0 PAL PULSE 1 1 0 1 PDC and VPS automatic recognition 2 1 1 1 0 PDC and VPS automatic recognition 3 1 1 1 1 PDC and VPS automatic recognition 4 Note: All registers are cleared to 0 when the IC is reset by the RST pin. |
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