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LC75808E Folha de dados(PDF) 7 Page - Sanyo Semicon Device |
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LC75808E Folha de dados(HTML) 7 Page - Sanyo Semicon Device |
7 / 39 page No. 6370 -7/39 LC75808E, 75808W Pin Pin No. Function Active I/O Handling LC75808E LC75808W when unused S1 to S60 3 to 62 1 to 60 Segment driver outputs. — q q OPEN COM1 to COM10 72 to 63 70 to 61 Common driver outputs. — q q OPEN KS1 to KS6 73 to 78 71 to 76 — O OPEN KI1 to KI5 79 to 83 77 to 81 Key scan inputs. H I GND These pins have built-in pull-down resistors. P1 to P4 84 to 87 82 to 85 General-purpose output ports. — q q OPEN OSC 97 95 — I/O VDD CE 100 98 HI CL 1 99 I GND DI 2 100 —I DO 99 97 — O OPEN INH 98 96 LI VDD TEST 96 94 This pin must be connected to ground. — I — VLCD090 88 — 0 OPEN VLCD191 89 — I OPEN VLCD292 90 — I OPEN VLCD393 91 — I OPEN VLCD494 92 — I GND VDD 88 86 —— — VLCD 89 87 —— — VSS 95 93 Power supply connection. Connect to ground. — — — Pin Functions Key scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE :Chip enable CL :Synchronization clock DI :Transfer data DO :Output data v Input that turns the display off, disables key scanning, and forces the general-purpose output ports low. • When INH is low (VSS): • Display off S1 to S60 = “L” (VLCD4). COM1 to COM10 = “L” (VLCD4). • General-purpose output ports P1 to P4 = low (VSS) • Key scanning is disabled: KS1 to KS6 = low (VSS) • All the key data is reset to low. • When INH is high (VDD): • Display on • The states of the general-purpose output ports can be set by the PC1 to PC4 control data. • Key scanning is enabled. However, serial data can be transferred when the INH pin is low. LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 (VLCD0 – VLCD4) voltage level externally. LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 (VLCD0 – VLCD4) voltage level externally. LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 (VLCD0 – VLCD4) voltage level externally. LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V, and VLCD4 must be in the range 0 V to 1.5 V, inclusive. Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V. LCD driver block power supply connection. Provide a voltage of between 7.0 and 11.0 V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 11.0 V when the circuit is not used. LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V. Also,external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. |
Nº de peça semelhante - LC75808E |
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Descrição semelhante - LC75808E |
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